Has been three years in the computer repair work, rely on the test card to determine the fault lies, so it collected some experience of the test card code, sent to share with you!
Hope seen that a good friend to help supplement the lack of local
Different motherboard BIOS, the test card test code is not the same, but the test card is not perfect, so he just give us a reference!
Code shows C0 C0: boot detection, has a bad motherboard BIOS failure or motherboard chip
C1: C1, this detects whether the memory through the stop is, however, but the motherboard fault suspect
C3: Memory Problems
D3, and D4: memory problems, but the motherboard memory slots is also possible, the majority of the AMD board, then the CPU fan out, tighten the CPU power test
25: 25 for the card or slot, generally clear the motherboard BIOS will be able to bright. Or changed graphics
26 or 2b: light machine, light machine to consider graphics
31: video card or slot
45: Graphics problem
00: just getting on the machine directly to the 00 or FF is a bad CPU or motherboard chip
FF: just machines directly to the 00 or FF is a bad CPU or the motherboard chip, it may be insufficient power supply
13: in AMI BIOS13 is normal
75: BIOS failure to reset the BIOS to
00: Boot Code Go to last display is normal for this bright machine
FF: The boot code Go to last show bright as normal for this machine
Now I write to you, tonight, think of the code under maintenance hope all my friends to help supplement !
Original: the detection of card brochures code meaning
Award BIOS Ami BIOS the Phoenix BIOS code or Tandy 3000 BIOS
00 shows the configuration of the system; upcoming control INI19 bootloader. .
01 processor test, the processor state to verify if the test fails, the loop is infinite. Processor register test about to begin, the non-maskable interrupt disabled soon. CPU register test in progress or failure.
02 to determine the diagnosis of the type (normal or manufacture). If the keyboard buffer containing the data will be invalid. Non-maskable interrupt is disabled; by delaying. CMOS write / read in progress or failure.
03 Clear 8042 keyboard controller, the issued TESTKBRD command (AAH) has completed power-on delay. ROM BIOS check the parts in progress or failure.
04 8042 keyboard controller reset and verify TESTKBRD. Keyboard controller soft reset / power test. Programmable interval timer test in progress or failure.
05 If you continue to repeat the manufacturing test 1-5 obtained 8042 control of the state. Has determined that the soft reset / power; upcoming boot ROM. DMA in progress or failure such as preparing early.
06 circuit piece for the initial preparation, Disable video, parity, DMA circuit chip, as well as to clear the DMA circuit chip all page registers and CMOS shutdown byte. Start the ROM calculate the ROM BIOS checksum, and checks the keyboard buffer is cleared. Initial DMA page register read / write test in progress or failure.
07 processor test, to verify the CPU registers. ROM BIOS checksum normal keyboard buffer is cleared, the BAT (Basic Assurance Test) command is issued to the keyboard. .
08 CMOS timer for the initial preparation, the normal update cycle of the timer. Has been issued to the keyboard BAT command is about to be written to the BAT command. RAM update test in progress or failure.
09 EPROM checksum must be equal to zero before passing. To verify the basic assurance tests of the keyboard, and then verify the keyboard command byte. The first 64K RAM test in progress.
0A to make a video interface for the initial preparation. Issue a keyboard command byte code, and is about to write command byte data. The first 64K RAM chip or data line failure, shift.
0B TEST 8254 Channel 0. Write the keyboard controller command byte to be issued to the pins 23 and 24 blocked / unlock command. First 64K RAM odd / even logic failure.
0C to test the 8254 Channel 1. The keyboard controller pins 23 and 24 block / unlock; has issued a NOP command. A 64K the RAN address line failure.
0D 1, check the CPU speed and system clock to match. 2, check the controller chip has been programmed value is in line with the early set. 3, the video channel, if it fails, then the honking. Has to deal with NOP command; then Test CMOS stop to open the register. A 64K RAM parity failure
0E Test CMOS shutdown byte. CMOS closed for register read / write test; will calculate CMOS checksum. Initialize the input / output port address.
0F test extended CMOS. Calculated the CMOS checksum is written to the diagnostic bytes; CMOS start initial preparation. .
10 Test DMA channel 0. CMOS have been made to the initial preparation of the CMOS status register is about the date and time for the initial preparation. The first 64K RAM 0 fault.
11 Test DMA channel 1. The CMOS status register for the initial preparation, is about to disable DMA and interrupt controller. A fault of a 64DK RAM.
12 Test DMA page register. Disable DMA controller and interrupt controller 1 and 2; upcoming video display and port B for the initial preparation. A 64DK RAM 2 fault.
13 Test 8741 keyboard controller interface. The video display is disabled, the port B for the initial preparation; about to begin the circuit chip initialization / memory auto-detection. A 64DK RAM 3 fault.
14 test memory update trigger circuit. Circuit chip initialization / memory at automatically detect the end; 8254 timer test about to begin. A 64DK RAM 4 fault.
15 test the first 64K of system memory. 2-channel timer test half; 8254 Part 2 channel timer is about to complete the test. 5 failure of a 64DK RAM.
16 to establish the 8259 interrupt vector table. The end of the 2-channel timer test; 8254 1 channel timer is about to complete the test. The first 64DK RAM 6 fault.
17 alignment of the video input / output, equipped with video BIOS is enabled. The end of the channel 1 timer test; 8254 0 channel timer is about to complete the test. The first 64DK RAM seven of failure.
18 Test video memory, install the optional video through the BIOS, can bypass the. 0 channel timer end of the test; about to begin the update memory. The first 64DK RAM 8 fault.
19 test a channel interrupt controller (8259) mask bit. Has begun to update the memory, then will complete the update of the memory. The first 64DK RAM 9 of failure.
1A test channel 2 interrupt controller (8259) shielding. Are triggering memory to update the line, going to check 15 μs ON / OFF time. The first 64DK RAM 10 fault.
1B Test CMOS battery level. Complete test of the memory update time of 30 microseconds; about to start 64K memory tests. The first 64DK RAM 11 fault.
1C Test CMOS check sum. The first 64DK RAM 12 fault.
1D it is set CMOS configuration. The first 64DK RAM 13 fault.
1E Determination of the size of system memory, and compare it and CMOS values. The first 64DK RAM 14 fault.
1F test 64K memory to a maximum of 640K. The first 64DK RAM 15 fault.
20 measuring a fixed 8259 interrupt bits. Start a basic 64K memory test; about to test the address lines. Slave DMA register test in progress or failure.
21 to maintain the non-maskable interrupt (NMI) bits (parity or input / output channel checking). Address line test; about to trigger the parity. Master DMA register test in progress or failure.
22 Test 8259 interrupt function. End of the trigger parity; will start the serial data read / write test. The main interrupt mask register test in progress or failure.
23 Test protected mode 8086 virtually 8086 pages the way. The basic 64K serial data read / write tests are normal; about to start an interrupt vector initialization before any adjustments. Slave interrupt mask register test in progress or failure.
24 Determination of extended memory above 1MB. Any adjustments before vector initialization about to begin the interrupt vector of the initial preparation. Set ES segment address register registry into memory high-end.
25 test in addition to all the memory after the first 64K. Completion of the interrupt vector of the initial preparation; for the rotary intermittent read 8042 input / output port. Loaded with the interrupt vector in progress or failure.
26 Test protected mode exceptions. Reading the 8042 input / output port; upcoming rotary intermittent global data for the initial preparation. Open the A20 address line; to make parameters into addressing.
27 to determine the ultra-high-speed buffer memory control or shielding RAM. A full data the initial preparation to end; will move on to the interrupt vector after the initial preparation. Keyboard controller test in progress or failure.
28 to determine the control of ultra-high-speed buffer memory or a special 8042 keyboard controller. Completion of the interrupt vector after the initial preparation; about to adjust the order color. CMOS power failure / checksum calculation in progress.
29 to adjust the order color ways about it is set in color. CMOS configuration validity check is in progress.
2A so that the keyboard controller for the initial preparation. It is set the color mode, the forthcoming trigger parity before the ROM test. Home empty 64K memory.
2B so that the disk drive and controller for the initial preparation. Trigger the end of the parity; about to control the optional video ROM check required before any adjustments. Screen memory test in progress or failure.
2C check the serial port, and for the initial preparation. Complete processing before video ROM control; about to view optional video ROM and control. Screen the initial preparation is in progress or failure.
2D parallel port is detected, and for the initial preparation. Has completed the optional video ROM control, is about the control of any other processing after video ROM Reply. Screen retrace tests in progress or failure.
2E hard disk drive and controller for the initial preparation. To recover from processing after video ROM control; If not found necessary to EGA / VGA display memory read / write test. Detect the video ROM in progress.
2F detect math coprocessor, and for the initial preparation. Did not find the EGA / VGA; about to begin display memory read / write test. .
30 to establish the basic memory and extended memory. Through the display memory read / write test; upcoming scan. Screen can work.
31 detected from the C800: 0 to EFFF: 0 the choice of ROM, and make the initial preparation. The display memory read / write test or scan fails, the upcoming Another display memory read / write test. Monochrome monitor work.
32 pairs of COM / LTP / FDD / sound equipment, and other I / O chip on the motherboard programming to make it suitable for setting values. Another display memory read / write test; puts another display and scan. Color Monitor (40) can work.
33 the end of the video display inspection; will start using the adjustment switch and the actual card off of the test display type. Color Monitor (80) can work.
34 test display adapter; then set to display. The timer tick interrupt test in progress or failure.
35 to complete the set to display; about to check the BIOS ROM data area. Shutdown test in progress or failure.
36 check the BIOS ROM data area; about it is set the cursor of the power of information. A-20 gate failure.
Information of the cursor 37. Identify power it is set has been completed; about to show the power of information. Unexpected interruption in protection mode.
38 complete display power; about to read out the new cursor position. RAM test in progress or address failure> FFFFH.
39 has been read out to save the cursor position display reference string of information. .
3A. The end of the string of information display; upcoming found <ESC> information. Interval timer channel 2 test or failure.
3B OPTI circuit chip (486), the secondary cache for the initial preparation. Has been shown to found <ESC> information; virtual mode memory test about to begin. A daily calendar clock test in progress or failure.
3C establishment of a sign allowed to enter the CMOS setup. The serial port test in progress or failure.
3D Initialize keyboard / PS2 mouse / PnP device and memory nodes. Parallel port test in progress or failure.
3E attempt to open the L2 cache. . Math coprocessor test in progress or failure.
40 has begun to prepare a virtual way of testing; forthcoming from the video memory to test. Adjust the CPU speed, so that with the external clock to an exact match.
41 interrupt is turned on, initialization data in order to detect memory 0:0 transformation (interrupt controller or bad memory) from the video memory test after recovery; be prepared by the descriptor table. System plug-in board select failure.
42 shows the window to enter SETUP. The descriptor table is ready; upcoming virtual mode for memory test. Extended CMOS RAM failure.
43 If the Plug and Play BIOS, then the serial port, parallel port initialization. Into the virtual way; interrupt to be achieved for the diagnosis. .
44 has been achieved interrupt (if connected to the diagnostic switch; about to make the data for the initial preparation to check the memory in 0:0 reversal.) BIOS interrupt is initialized.
45 initialize math coprocessor. The data for the initial preparation; will check the memory in 0:0 reversal and to identify the size of system memory. .
46 test memory has returned; memory size calculation is completed, is about to write the page to test the memory. Check the read-only memory ROM version.
Try to write 47. Upcoming expanded memory page; about to 640K memory is written to the page. .
48 has been the basic memory written to the page; will determine more than 1MB of memory. Video inspection, CMOS reconfiguration.
49 to identify the the 1BM less memory and test; will determine more than 1MB of memory. .
4A. Find more than 1MB of memory and test; going to check the BIOS ROM data area. Initialization of the video.
4B BIOS ROM data area of the test end will check <ESC> and soft reset to clear memory above 1MB. .
4C. Clear than 1MB of memory (soft reset) will remove more than 1MB of memory. Shielded video BIOS ROM. .
4D has cleared more than 1MB of memory (soft reset); will save the memory size. .
4E detected an error; error message is displayed on the monitor and wait for customers to continue to press <F1>. Start a memory test: (no soft reset); will soon display the first 64K of memory tests. The copyright information is displayed.
4F to read and write soft and hard data, for DOS boot. Beginning to show the size of the memory being tested memory will make the update; serial and random memory test. .
50 the current time zone in the BIOS supervisor CMOS value to CMOS. To complete the test below 1MB memory; the size of upcoming high-speed memory for re-positioning and masking. CPU type and speed to the screen.
51 test memory above 1MB. .
52 all ISA read-only memory ROM is initialized, and eventually assigned to PCI IRQ number initialization. Has completed more than 1MB of memory testing; will be ready to return to a real address. Enter the keyboard detection.
53 If it is not Plug and Play BIOS, initialize serial, parallel and set value. Save the CPU registers and memory size, enter the real site. .
54 successfully open a real address; about to recover the saved registers in preparation for shutdown. Scanning against key "
55 registers recovered, will disable gate A-20 address lines. .
56 successfully disable the A-20 address lines; going to check the BIOS ROM data area. The end of the keyboard test.
57 BIOS ROM data area check in half; continue. .
58 BIOS ROM data area check over; clear discovery <ESC> information. Set non-interrupt test.
59. Clear <ESC> information; information display; about to start DMA and interrupt controller test. .
5A .. show press "F2" key setup.
5B. Test base memory address.
5C .. 640K base memory test.
60 set the hard disk boot sector virus protection. DMA page register test; about to test the video memory. Test the extended memory.
61 shows the system configuration table. The end of the video memory test; upcoming DMA # 1 base register test. .
62 system boot using interrupt 19H. DMA # 1 base register test; upcoming DMA # 2 register test. Test extended memory address lines.
63 DMA # 2 base register test; about to check the BIOS ROM data area. .
64 BIOS ROM data area check in half, to proceed. .
65 BIOS ROM data area check over; will DMA unit 1 and 2 programming. .
66 DMA unit 1 and 2 programming over; about to No. 59, interrupt controller for the initial preparation. Cache registry to optimize the allocation.
67.8259 initial preparation has ended; about to start the keyboard test. .
68 .. External Cache and CPU internal cache work.
6A .. test and display the value of external Cache.
6C .. the display is masked content.
6E .. display subsidiary configuration information.
70 .. detected the error code to the screen display.
72 .. test configuration error.
74 .. to test real-time clock.
76 .. scan the keyboard error.
7A .. lock the keyboard.
7C .. set the hardware interrupt vector.
7E .. test whether to install the mathematical processor.
80 keyboard test, is clear and check there is no key stuck and about to make the keyboard recovery. Close the programmable input / output devices.
81. Identify key keyboard error recovery stuck; be issued to test the command of the keyboard control port. .
82 keyboard controller interface test over, about to write command byte and for the initial preparation of the circular buffer. Testing and installation of fixed RS232 interface (serial port).
83. Command byte has been written, has completed the initial preparation of the global data; going to check there is no key lock. .
84 check locked key will check the memory with CMOS mismatch. Testing and installation of fixed parallel port.
85 to check the size of the memory; about to display soft error and password, or bypass arrangements. .
86 to check the password; upcoming programming before the by-pass arrangement. Re-open programmable I / O devices and the detection of fixed I / O if there are conflicts.
87 complete arrangements for the pre-programming; will CMOS scheduled programming. .
88 recover from the CMOS Scheduler to clear the screen; upcoming behind the programming. Initialize BIOS Data Area.
89 completion of the programming arrangements; power screen information to be displayed. .
8A. Display the first screen of information. Be extended BIOS data area is initialized.
8B. Show Information: about to shield the main and video BIOS. .
8C. Successfully shield the main and video BIOS, began CMOS arrangement any option programming. The floppy drive controller initialization.
8D. Have arranged optional programming, then check slip of the mouse and the initial preparation. .
8E. Detect the mouse and the completion of the initial preparation; about to hard and floppy disks reset. .
8F. The floppy disk has to check the disk for the initial preparation, and then with a floppy disk. .
90. The end of the floppy disk configuration; will test the existence of the hard disks. The hard disk controller is initialized.
91 hard disks exist end of the test; then configure the hard disk. The local bus hard disk controller initialization.
92 hard disk configuration is complete; about to check the BIOS ROM data area. Jump to the user path.
93 BIOS ROM data area have been checked half; continue. .
94 of the BIOS ROM data area check is completed, it is set to basic and extended memory size. Turn off the A-20 address lines.
95 displayed in response to the mouse and hard disk support 47 to adjust the size of a good memory; will test the memory. .
96 test display memory recovery; upcoming C800: 0 optional ROM control prior to the initial preparation. The ES segment "registry cleared.
97. C800: 0 optional ROM control before any initial ready to end, followed by optional ROM check and control. .
98 optional ROM control complete; about to carry out any processing required after optional ROM reply control. Find the ROM selection.
99 required after optional ROM test any initial ready to end; about to establish the timer data area and printer base address. .
9A. It is set to return after the timer and printer base address of the operation; that it is set to RS-232 base address. Shielded ROM option.
9B. Returned after the RS-232 base address; upcoming initial preparation of the coprocessor test. .
9C. Co-processor test required before the initial preparation of an end; then the co-processor for the initial preparation. The establishment of the power saving management.
9D. Coprocessor make initial preparations for the upcoming initial preparation of any coprocessor test. .
9E. Complete coprocessor after the initial preparation, will check extended keyboard, keyboard identifier, and a digital lock. The open hardware interrupt.
9F. Check extended keyboard, it is set identification mark, the digital lock is turned on or off, keyboard recognize the command will be issued. .
A0. Issued keyboard identification command; recovery is about to make the keyboard identification. Set the time and date.
A1 keyboard identification recovery; followed by high-speed buffer memory test. .
A2. The end of the cache memory test; is about to display any soft errors. Check the keyboard lock.
A3 soft error display is completed; about to tune to hit the keyboard rate. .
A4. And adjust the hit rate of the keyboard, the forthcoming memory wait states. Keyboard to re-enter the initialization of the rate.
A5. Memory wait state finalized; then clear the screen. .
A6. Screen has been cleared; about to start parity and non-maskable interrupt. .
A7. Enable non-maskable interrupts and parity; about to control an optional ROM at E000: 0 required for any initial preparation. .
A8. Control ROM ready to end before the initial E000: 0, then the control E000: 0 required after the initial preparation. Clear the "F2" key prompt.
A9 from the control E000: ROM, return about control E000: 0 optional ROM required for any initial preparation. .
AA E000: Control optional ROM after the initial preparation of the end; about to show the configuration of the system. Scanning "F2" key blow.
AC .. enter settings.
AE .. clear the power-on self-test mark.
B0 .. check the non-critical error.
B2 .. Power On Self Test to complete ready to enter the operating system boot.
B4 .. the buzzer sounds.
B6 .. detection of password settings (optional).
Look .. to clear the full description of the table.
BC .. Clear parity check value.
BE program default values into the control chip, in line with the modulation binary default value table. Clear screen (optional).
BF Test CMOS establish value. Detect the virus, suggesting that to do a data backup.
C0 initialize the cache. Using interrupt 19 test guide.
C1 memory self-test. Find the boot sector of the "55" "AA" tag.
C3 a 256K memory test. ..
C5 copied from ROM BIOS for quick self-test. ..
C6 cache self-test. ..
CA the detection Micronies speeding buffer memory (if present), and for the initial preparation. ..
CC off non-maskable interrupt the processor. ..
EE processor unexpected exceptions. ..
FF to give INI19 boot loader control, the motherboard OK.
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